The invention relates to a method for forming an opening in a mold layer and to methods for producing storage capacitors for dynamic semiconductor memory cells.
Dynamic semiconductor memory cells for DRAMs (Dynamic Random Access Memories) include a storage capacitor for storing the data and a selection transistor for addressing the storage capacitor.
Data are stored by charging or discharging the storage capacitor by using the selection transistor. The selection transistors of the DRAM memory cells are formed in a monocrystalline silicon substrate. In DRAM memory cells with a stacked capacitor, the storage capacitors are formed in a mold layer that covers a substrate surface of the silicon substrate. In DRAM memory cells with a trench capacitor, the capacitors are formed along trenches that are introduced into the semiconductor substrate from the substrate surface.
In order to obtain high packing densities in a DRAM semiconductor circuit, the projection area of the storage capacitor onto a planar substrate surface is minimized.
The charge stored on the capacitor changes owing to various leakage current mechanisms even when the memory cell is not addressed. In order to prevent a complete discharge of the capacitor, the charge is periodically refreshed in refresh cycles. The number of refresh cycles can be reduced if the capacitance of the storage capacitor is as large as possible. The requirement of a largest possible electrode surface area in conjunction with the—likewise sought—minimum projection area on the horizontal substrate surface give rise to the requirement for a largest possible vertical extent of the capacitor electrodes.
Stacked capacitors are usually formed in a mold layer that is applied to the substrate surface. Openings are etched into the mold layer. A first electrode, a capacitor dielectric and a second electrode are applied successively in the openings or along the inner walls of the openings. For this purpose, openings having an aspect ratio of depth to width of greater than 40:1 are required for DRAMs which are fabricated with a minimum lithographic feature size of less than 50 nm.
Present-day etching methods only enable aspect ratios of up to 25:1 for mold layers composed of silicon oxides in conjunction with sufficient profile fidelity and dimensional accuracy of the cross section of the etching at the trench bottom.
In order to enlarge the electrode areas, the stacked capacitors are also constructed from partial capacitors with a smaller vertical extent that are arranged one above another in a plurality of successive partial processes. What is disadvantageous about such methods is their increased process complexity.
In order to produce trench capacitors, an etching mask (hard mask), generally silicon oxide or nitride, is applied on a substrate surface of the semiconductor substrate. The etching mask is patterned by a photolithographic process and an opening is produced in the etching mask in the process. The opening is transferred into the underlying semiconductor substrate with the highest possible dimensional accuracy and profile fidelity in a further etching process. Since the etching mask is consumed during the etching of the trench for the capacitor in the semiconductor substrate, the etching mask has to be provided with a thickness which is all the higher, the deeper the trench etching into the semiconductor substrate is to be performed.
Restrictions similar to those for the opening for a stacked capacitor in a mold layer arise for the opening in the etching mask. The depth of a trench for a trench capacitor is thus limited by the maximum aspect ratio which can be realized for the opening in the etching mask.
The use of alternative etching mask materials requires comprehensive preliminary investigations and increases the process complexity.
For these and other reasons, there is a need for the present invention.